This invention relates to a semiconductor memory, and to a technique which is effective when utilized for a dynamic RAM (random access memory) incorporating therein an address counter circuit for automatic refresh, for example.
When a figure is displayed on a CRT (cathode ray tube), data in the form of logic "0" and logic "1" in accordance with dots constituting the figure is written in advance into memory. The figure is displayed by sequentially reading out the data written into the memory in synchronism with the CRT raster scan timing. When a dynamic RAM is used as a refresh memory for displaying such a figure (or character), address signals must be sequentially generated from an external control circuit such as a micro-processor or the like.
The inventor of this invention developed a semiconductor memory which can easily effect a read-out operation in a predetermined sequence such as that with the refresh memory described above. As an example of the prior art references describing in detail the dynamic RAM, mention can be made of Japanese Patent Laid-Open No. 82282/1982.